臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立中山大學	2005-07	A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition	Tso-Bing Juang;Shen-Fu Hsiao;Ming-Yu Tsai;Jeng-Hsiung Jan
國立中山大學	2002-08	A High-Performance Function Generator for Multiplier-Based Arithmetic Operations	Tso-Bing Juang; Jeng-Hsin Jan; Ming-Yu Tsai; Shen-Fu Hsiao
國立中山大學	2001-08	A Multiplier-Based Arithmetic Function Generator for Digital Signal Processing Applications	Shen-Fu Hsiao; Tso-Bing Juang; Jeng Hsium Jan; Ming Yu Tsai
國立中山大學	2006-12	An Automatic Cache Generator Based on Content-Addressable Memory	Shen-Fu Hsiao; Sze-Yun Lin; Tze-Chorng Cheng; Ming-Yu Tsai
國立中山大學	2005-5	An Efficient Pass-Transistor-Logic Synthesizer Using Multiplexers and Inverters Only	Shen-Fu Hsiao; Ming-Yu Tsai; Ming-Chih Chen; Chia-Sheng Wen
國立中山大學	2003-08	Architectural Optimization for the forward and Inverse MixColumn Operations in Rijndael AES	Ming-Chih Chen; Shen-Fu Hsiao; Ming-Yu Tsai
國立中山大學	2008-05	Area-Oriented Pass-Transistor Logic Synthesis Using Buffer Elimination and Layout Compaction	Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen
國立中山大學	2003-12	Design of Fixed-Length Multipliers Using Radix-2 Signed-Digit Redundant Numbers	Tso-Bing Juang; Shen-Fu Hsiao; Ming-Yu Tsai
國立中山大學	2006-12	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits	Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen
國立中山大學	2002-08	High-Performance Logic Synthesis Based on Pass-Transistor Logic	Ming-Yu Tsai; Chia-Sheng Wen; Shen-Fu Hsiao

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